AMD shows off the guts of its first ARM server chip

First unveiled in January, AMD today gave a detailed look at its first ARM-based server processor, the Opteron A1100 "Seattle."

Seattle has eight 64-bit ARM Cortex-A57 cores arranged into four pairs, with each pair sharing 1MB of level 2 cache. All eight cores share an 8 MB level 3 cache. There are two memory controllers, supporting both DDR3 and DDR4, enabling a total of 128GB ECC memory in total.

These cores all share a set of I/O options. The system-on-a-chip has 8 lanes of PCIe 3.0 for expansion cards and 8 lanes of SATA revision 3.0 for storage. Network connectivity comes from two 10GBASE-KR controllers. (10GBASE-KR is a short-range specification designed for copper connections to backplanes in blade servers and modular routers.)

The SoC also includes a couple of other processing elements, such as a cryptographic coprocessor that accelerates AES, elliptic curve, and RSA encryption, SHA hashing, and zlib compression and decompression.

The other processing element is the "system control processor" (SCP). This is a Cortex A5 processor with its own RAM, ROM, and I/O system—a system-on-a-chip integrated into a larger system-on-a-chip. The SCP controls the chip's power management, performs initial configuration and booting, and can be used for system management functions. It has its own external connectivity, including gigabit Ethernet, I²C, and serial, and uses ARM's TrustZone technology to enable the SCP to be securely isolated from software running on the eight A57 cores.

For system developers wanting to get started with Seattle, AMD has a reference micro-ATX board housing one Seattle processor, four DDR3 slots, and connectors for the A1100's various connectivity options: a PCIe x8 slot, eight SATA3 ports, two 10GBASE-T connectors, and I²C and UARTs for the SCP. The reference system puts this board in a 2U rack-mount chassis with a power supply and space for eight hard drives.