Now you can DIY a RISC-V SoC with SiFive’s “hassle-free” process
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SiFive announced free downloads and tools for rapid evaluation of its “fully synthesizable” RISC-V based Coreplex E31 and E51 cores on a $99 FPGA dev board. The 64-bit RISC-V ISA (instruction set architecture) was developed at the University of California, Berkeley in 2010, and subsequently became the basis of a University of Cambridge sponsored lowRISC […]
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